1. Field of the Invention
The present invention relates to a gate driver, and more particularly, to a gate driver capable of outputting a reliable output signal and a display device having the gate driver.
2. Description of the Related Art
A display device for displaying an image by controlling pixels arranged in a matrix has been widely used. A liquid crystal display device (LCD) and an organic light emitting diode device (OLED) are examples of such display devices.
Such display devices include a display panel having pixels arranged in a matrix, a gate driver for scanning pixels line by line, and a data driver for supplying an image data. Recently, a display device having a gate driver and/or a data driver embedded on the display panel has developed to achieve a low manufacturing cost, simplify the manufacturing process, and be light and slim.
When manufacturing the display panel, the gate driver and/or the data driver are/is manufactured concurrently. That is, a plurality of thin film transistors (TFTs) are provided to control each of the pixels in the display panel, and the gate driver and/or the data driver can be manufactured through the same semiconductor process as the TFT. Each of the drivers includes a plurality of shift registers for outputting output signals. For example, when the display panel has ten gate lines, ten shift registers are provided to supply their output signals to the ten gate lines, respectively.
FIG. 1 is a block diagram of a related art gate driver. Referring to FIG. 1, the related art gate driver includes a plurality of shift registers SRC1 through SRC[N+1]. The shift registers include N shift registers SRC1 through SRC[N] corresponding to N gate lines, and a dummy shift register SRC[N+1]. The shift registers SRC1 through SRC[N+1] are connected in cascade with each other. That is, an output terminal OUT of each shift register is connected to a set terminal SET of the next shift register. Each of the shift registers SRC1 through SRC[N] other than the dummy shift register SRC[N+1] is reset by the output signal of its next shift register. The output of the dummy shift register SRC[N+1] is used to reset the previous shift register SRC[N].
The first shift register SRC1 is set by a pulse start signal STV. The pulse start signal is a pulse synchronized with a vertical synch signal Vsync. Each of the shift registers SRC2 through SRC[N+1] is set by an output signal from the preceding shift register. When there are N gate lines, output signals GOUT1 through GOUT[N] of the N shift registers are connected to the corresponding gate lines (not shown). The output signal GOUT[N+1] of the dummy shift register SRC[N+1] is not connected to any gate line.
A first clock CKV is supplied to the odd-numbered shift registers SRC1,SRC3, . . . , and a second clock CKVB is supplied to the even-numbered shift registers SRC2, SRC4, . . . . Here, a phase of the first clock CKV is opposite to that of the second clock CKVB. The first clock CKV is simultaneously applied to the odd-numbered shift registers SRC1, SRC3, . . . , and the second clock CKVB is simultaneously applied to the even-numbered shift registers SRC2, SRC4,. . . .
The pulse start signal STV is applied to the first shift register SRC1 when the second clock CKVB is high. The shift registers SRC1 through SRC[N] output the respective output signals GOUT1 through GOUT[N], respectively, in synchronization with the first clock CKV or the second clock CKVB.
Accordingly, each of the shift registers SRC1 through SRC[N] is set by the output signal of its previous shift register and outputs the output signal in synchronization with the first or second clocks CKV or CKVB, and then is reset by the output signal of its next shift register. However, since there is no shift register next to the dummy shift register SRC[N+1], the dummy shift register SRC[N+1] is reset by its own output signal GOUT[N+1].
FIG. 2 is a circuit diagram of the related art shift register of FIG. 1. FIG. 3 is a waveform diagram of driving signals for driving the related art shift register of FIG. 2. Since the shift registers illustrated in FIG. 1 have the identical structure to one another, only the first shift register SRC1 will be described for convenience.
Referring to FIGS. 2 and 3, when the pulse start signal STV is high, the first clock CKV and the second clock CKVB are low and high, respectively. Also, the first clock CKV and the second clock CKVB are at a high state at each clock period. The first shift register SRC1 is set by a high state of the pulse start signal STV during a high state of the second clock CKVB. That is, when the pulse start signal STV is applied, a Q node is charged to a voltage of the pulse start signal STV. A first transistor M1 is turned on by the charged Q node. Then, a QB node is discharged by a voltage difference (VDD−VSS) between a first power supply voltage and a second power supply voltage. Consequently, a low voltage of the QB node is maintained by a ratio of a resistance R1 of a first transistor M1 to a resistance R6 of a sixth transistor M6.
During a high state of the first clock CKV, a first output signal GOUT1 is outputted in response to the first clock CKV. That is, when the first clock CKV is applied to the second transistor M2, a bootstrapping is caused by a drain-gate capacitance in a second transistor M2, and thus the Q node is charged with a voltage higher than that of the charged pulse start signal STV. Accordingly, the second transistor M2 is turned on and thus the first clock CKV is outputted as the first output signal GOUT1.
During the next period of the second clock CKVB, the first shift register SRC1 is reset by the second output signal GOUT2 of its next shift register SRC2. That is, a fifth transistor M5 is turned on by the second output signal GOUT2 of the shift register SRC2, and the Q node is discharged by a first power supply voltage VSS passing through the fifth transistor M5. Additionally, the first transistor M1 is turned off by the discharged Q node, and the QB node is charged with the second supply voltage VDD passing through the sixth transistor M6, so that third and fourth transistors M3 and M4 are turned on by the charged QB node. Accordingly, the Q node is easily discharged by the first power supply voltage VSS passing through the turned-on fourth transistor M4. In this case, most of the output signal GOUT1 is discharged through a source-drain path of the second transistor M2, and the remaining output signal GOUT1 is discharged through the first power supply voltage VSS by the turned-on third transistor M3. However, an undesired output signal may be generated from each of the shift registers SRC1 through SRC[N] in the related art gate driver.
FIG. 4 is a graph illustrating a plurality of undesired output signals outputted in the related art gate driver. As illustrated in FIG. 4, when an Nth output signal GOUT[N] is outputted from the Nth shift register SRC[N] by the second clock CKVB, second and fifth output signals GOUT2 and GOUT4 are also outputted respectively from even-numbered shift registers SRC2 and SRC4 to which the second clock CKVB is applied. That is, in addition to a desired output signal, a plurality of undesired output signals may be outputted during one clock period.
Specifically, the shift registers SRC1 through SRC[N] output the corresponding output signals GOUT1 through GOUT[N] once per frame period. For example, the fourth shift register SRC4 outputs the fourth output signal GOUT4 during a period of the second clock CKVB period, but does not output the output signal during the remaining part (90%) of the frame period. For this purpose, the third transistor M3 of the fourth shift register SRC4 must be turned on and thus the QB node connected to the third transistor M3 always maintains a high state during the remaining period. When this operation is repeated for each frame, the third and fourth transistors M3 and M4 are degraded. Accordingly, the threshold voltages of the third and fourth transistors M3 and M4 are shifted and thus the transistors M3 and M4 cannot be easily turned off. In the worst case, the fourth transistor M4 is not turned off and thus the Q node is not reset. In this case, the output signal is outputted at an undesired time by the first or second clock CKV or CKVB.
Taking into consideration all the shift registers SRC1 through SRC[N], when the Nth output signal GOUT[N] is outputted from the Nth shift register SRC[N] by the second clock CKVB, the second and fifth output signals GOUT2 and GOUT4 are also outputted respectively from even-numbered shift registers SRC2 and SRC4 to which the second clock CKVB is applied. This causes the device to malfunction, causing for example screen flickering, thus greatly degrading the reliability of the display.